library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Entity declaration
entity reg_rw_mux2to1 is
    Port (
        sel : in STD_LOGIC; -- 1-bit select input
        d0  : in  STD_LOGIC_VECTOR (1 downto 0); -- Data input 0
        d1  : in  STD_LOGIC_VECTOR (1 downto 0); -- Data input 1
        y   : out STD_LOGIC_VECTOR (1 downto 0)  -- Output
    );
end reg_rw_mux2to1;

-- Architecture definition
architecture Behavioral of reg_rw_mux2to1 is
begin
    process(sel, d0, d1)
    begin
        case sel is
            when '0' =>
                y <= d0;
            when '1' =>
                y <= d1;
            when others =>
                y <= "00"; 
        end case;
    end process;
end Behavioral;